/*!
    \file    change log.txt
    \brief   change log for GD32E51x firmware

    \version 2025-08-08, V1.3.0, firmware for GD32E51x
*/

/*
    Copyright (c) 2024, GigaDevice Semiconductor Inc.

    Redistribution and use in source and binary forms, with or without modification, 
are permitted provided that the following conditions are met:

    1. Redistributions of source code must retain the above copyright notice, this 
       list of conditions and the following disclaimer.
    2. Redistributions in binary form must reproduce the above copyright notice, 
       this list of conditions and the following disclaimer in the documentation 
       and/or other materials provided with the distribution.
    3. Neither the name of the copyright holder nor the names of its contributors 
       may be used to endorse or promote products derived from this software without 
       specific prior written permission.

    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
OF SUCH DAMAGE.
*/

******************* V1.3.0 2025-08-08 ******************************************************************************************
______________________Common______________________________________________________________________________________________
Fix file:
/fw3233/GD32E51x_Firmware_Library/Firmware/CMSIS/GD/GD32E51x/Source/system_gd32e51x.c
fix reason:
frequence modify
V1.2.0:
none
V1.3.0:
                                
/* The following is to prevent Vcore fluctuations caused by frequency switching. 
   It is strongly recommended to include it to avoid issues caused by self-removal. */
#define RCU_MODIFY_UP(__delay)  do{                                     \
                                      volatile uint32_t i,reg;            \
                                      if(0 != __delay){                   \
                                          for(i=0; i<__delay; i++){       \
                                          }                               \
                                          reg = RCU_CFG0;                 \
                                          reg &= ~(RCU_CFG0_AHBPSC);      \
                                          reg |= RCU_AHB_CKSYS_DIV2;      \
                                          RCU_CFG0 = reg;                 \
                                          for(i=0; i<__delay; i++){       \
                                          }                               \
                                          reg = RCU_CFG0;                 \
                                          reg &= ~(RCU_CFG0_AHBPSC);      \
                                          reg |= RCU_AHB_CKSYS_DIV1;      \
                                          RCU_CFG0 = reg;                 \
                                      }                                   \
                                  }while(0)


Fix file:
../GD32E51x_Firmware_Library/Template/gd32e51x_it.c
fix reason:ECC errors will not enter the NMI handler, modified
V1.1.0:
NONE
V1.2.0:
delete all ECC NMI handler content
_________________________________________________________________________________________________________________________________



______________________I2C____________________________________________________________________________________________

Fix file:
/fw3233/GD32E51x_Firmware_Library/Firmware/GD32E51x_standard_peripheral/Include/gd32e51x_i2c.h
/fw3233/GD32E51x_Firmware_Library/Firmware/GD32E51x_standard_peripheral/Source/gd32e51x_i2c.c
fix reason:
the configuration width of byte_number is 8 bit，the parameter can accept an input data width of 32 bits. 
V1.2.0:
void i2c_transfer_byte_number_config(uint32_t i2c_periph, uint32_t byte_number)
{
    I2C2_CTL1(i2c_periph) &= (uint32_t)(~I2C2_CTL1_BYTENUM);
    I2C2_CTL1(i2c_periph) |= (uint32_t)(byte_number << CTL1_BYTENUM_OFFSET);
}
V1.3.0:
void i2c_transfer_byte_number_config(uint32_t i2c_periph, uint8_t byte_number)
{
    I2C2_CTL1(i2c_periph) &= (uint32_t)(~I2C2_CTL1_BYTENUM);
    I2C2_CTL1(i2c_periph) |= (uint32_t)((uint32_t)byte_number << CTL1_BYTENUM_OFFSET);
}

Fix file:
/fw3233/GD32E51x_Firmware_Library/Firmware/GD32E51x_standard_peripheral/Include/gd32e51x_i2c.h
/fw3233/GD32E51x_Firmware_Library/Firmware/GD32E51x_standard_peripheral/Source/gd32e51x_i2c.c
fix reason:
delete i2c_nack_disable, NACKEN not support clear by software. 
V1.2.0:
    \brief      generate an ACK in slave mode
    \param[in]  i2c_periph: I2Cx(x=2)
    \param[out] none
    \retval     none
*/
void i2c_nack_disable(uint32_t i2c_periph)
{
    I2C2_CTL1(i2c_periph) &= ~I2C2_CTL1_NACKEN;
}

/*!
V1.3.0:
NONE
__________________________________________________________________________________________________________________________

______________________PMU____________________________________________________________________________________________

Fix file:
/fw3233/GD32E51x_Firmware_Library/Firmware/GD32E51x_standard_peripheral/Source/gd32e51x_pmu.c
fix reason:
pmu_to_sleepmode MODIFY
V1.2.0:
void pmu_to_sleepmode(uint8_t sleepmodecmd)
{
    /* clear sleepdeep bit of Cortex-M33 system control register */
    SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);

    /* select WFI or WFE command to enter sleep mode */
    if(WFI_CMD == sleepmodecmd) {
        __WFI();
    } else {
        __WFE();
        __WFE();
    }
}
V1.3.0:
void pmu_to_sleepmode(uint8_t sleepmodecmd)
{
    /* clear sleepdeep bit of Cortex-M33 system control register */
    SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);

    /* select WFI or WFE command to enter sleep mode */
    if(WFI_CMD == sleepmodecmd) {
        __WFI();
    } else {
        __SEV();
        __WFE();
        __WFE();
    }
}
__________________________________________________________________________________________________________________________

______________________CAN____________________________________________________________________________________________

Fix file:
/fw3233/GD32E51x_Firmware_Library/Firmware/GD32E51x_standard_peripheral/Source/gd32e51x_can.c
fix reason:
When the number of bytes sent by CAN exceeds 8, the frame sent by CAN to the bus will have a problem.

V1.2.0:
#ifdef GD32E518
    if(CAN_FDF_CLASSIC == transmit_message->fd_flag) {
        /* set the data length */
        CAN_TMP(can_periph, mailbox_number) &= ~(CAN_TMP_DLENC | CAN_TMP_ESI | CAN_TMP_BRS | CAN_TMP_FDF);
        CAN_TMP(can_periph, mailbox_number) |= transmit_message->tx_dlen;
        /* set the data */
V1.3.0:
#ifdef GD32E518
    if(CAN_FDF_CLASSIC == transmit_message->fd_flag) {
        /* set the data length */
        CAN_TMP(can_periph, mailbox_number) &= ~(CAN_TMP_DLENC | CAN_TMP_ESI | CAN_TMP_BRS | CAN_TMP_FDF);
        /* Classic CAN frame data length does not exceed 8 */
        if (transmit_message->tx_dlen > 8U) {
            transmit_message->tx_dlen = 8U;
        }
		
Fix file:
/fw3233/GD32E51x_Firmware_Library/Firmware/GD32E51x_standard_peripheral/Include/gd32e51x_can.h
fix reason:
added a pre-compile definition switch for EPRT

V1.2.0:
NONE
V1.3.0:
#ifndef GD32EPRTxxA
__________________________________________________________________________________________________________________________

______________________ENET_______________________________________________________________________________________________
Fix file:
/fw3233/GD32E51x_Firmware_Library/Firmware/GD32E51x_standard_peripheral/Source/gd32e51x_enet.c
fix reason: 
Add the precompiled macro defined (GD32EPRTxxA) to support the GD32EPRTxxA series.

V1.2.0:
#if defined(GD32E51X_CL) || defined(GD32E518)

V1.3.0:
#if defined(GD32E51X_CL) || defined(GD32E518) || defined (GD32EPRTxxA)





__________________________________________________________________________________________________________________________


______________________GPIO_______________________________________________________________________________________________
Fix file:
/fw3233/GD32E51x_Firmware_Library/Firmware/GD32E51x_standard_peripheral/Include/gd32e51x_gpio.h
fix reason: 
ADD ENET_PHY_SEL and ENET_REMAP AFIO PCF0

V1.2.0:
NONE

/* AFIO_PCFB */
#define AFIO_PCFB_PB0_AFCFG              BIT(0)              /*!< PB0 AF function configuration bit */
V1.3.0:
#define AFIO_PCF0_ENET_REMAP             BIT(21)             /*!< ethernet MAC I/O remapping */
#define AFIO_PCF0_ENET_PHY_SEL           BIT(23)             /*!< ethernet MII or RMII PHY selection */

Fix file:
/fw3233/GD32E51x_Firmware_Library/Firmware/GD32E51x_standard_peripheral/Include/gd32e51x_gpio.c
fix reason: 
E513 gpio AF do not support USBHS and CAN2

V1.2.0:
/*!
    \brief      configure AFIO port alternate function
    \param[in]  afio_function: select the port AFIO function
                only one parameter can be selected which are shown as below:
      \arg        AFIO_PA1_TIMER14_CFG：configure PA1 alternate function to TIMER14     
      \arg        AFIO_PA2_CMP1_CFG: configure PA2 alternate function to CMP1
      \arg        AFIO_PA2_TIMER14_CFG: configure PA2 alternate function to TIMER14
      \arg        AFIO_PA3_USBHS_CFG: configure PA3 alternate function to USBHS
      \arg        AFIO_PA3_TIMER14_CFG: configure PA3 alternate function to TIMER14
      \arg        AFIO_PA5_USBHS_CFG: configure PA5 alternate function to USBHS
      \arg        AFIO_PA6_TIMER15_CFG: configure PA6 alternate function to TIMER15
      \arg        AFIO_PA7_TIMER16_CFG: configure PA7 alternate function to TIMER16
      \arg        AFIO_PA8_I2C2_CFG: configure PA8 alternate function to I2C2
      \arg        AFIO_PA8_SHRTIMER_CFG: configure PA8 alternate function to SHRTIMER
      \arg        AFIO_PA9_CAN2_CFG: configure PA9 alternate function to CAN2
      \arg        AFIO_PA9_I2C2_CFG: configure PA9 alternate function to I2C2
      \arg        AFIO_PA9_SHRTIMER_CFG: configure PA9 alternate function to SHRTIMER
      \arg        AFIO_PA9_TIMER14_CFG: configure PA9 alternate function to TIMER14 
V1.3.0:
/*!
    \brief      configure AFIO port alternate function
    \param[in]  afio_function: select the port AFIO function
                only one parameter can be selected which are shown as below:
      \arg        AFIO_PA1_TIMER14_CFG：configure PA1 alternate function to TIMER14     
      \arg        AFIO_PA2_CMP1_CFG: configure PA2 alternate function to CMP1
      \arg        AFIO_PA2_TIMER14_CFG: configure PA2 alternate function to TIMER14
      \arg        AFIO_PA3_USBHS_CFG: configure PA3 alternate function to USBHS         Note: USBHS AF do not support in GD32E513
      \arg        AFIO_PA3_TIMER14_CFG: configure PA3 alternate function to TIMER14
      \arg        AFIO_PA5_USBHS_CFG: configure PA5 alternate function to USBHS         Note: USBHS AF do not support in GD32E513
      \arg        AFIO_PA6_TIMER15_CFG: configure PA6 alternate function to TIMER15
      \arg        AFIO_PA7_TIMER16_CFG: configure PA7 alternate function to TIMER16
      \arg        AFIO_PA8_I2C2_CFG: configure PA8 alternate function to I2C2
      \arg        AFIO_PA8_SHRTIMER_CFG: configure PA8 alternate function to SHRTIMER
      \arg        AFIO_PA9_CAN2_CFG: configure PA9 alternate function to CAN2           Note: CAN2 AF do not support in GD32E513
      \arg        AFIO_PA9_I2C2_CFG: configure PA9 alternate function to I2C2
      \arg        AFIO_PA9_SHRTIMER_CFG: configure PA9 alternate function to SHRTIMER
      \arg        AFIO_PA9_TIMER14_CFG: configure PA9 alternate function to TIMER14



__________________________________________________________________________________________________________________________


______________________USB_______________________________________________________________________________________________
Fix file:
/fw3233/GD32E51x_Firmware_Library/Firmware/GD32E51x_usbd_library/class/device/msc/Source/usbd_msc_scsi.c
fix reason: 
There is a problem with the code format, modify the code, modify the offset of the variable.


V1.2.0:
void scsi_sense_code (usb_dev *udev, uint8_t lun, uint8_t skey, uint8_t asc)
{
    usbd_msc_handler *msc = (usbd_msc_handler *)udev->class_data[USBD_MSC_INTERFACE];

    msc->scsi_sense[msc->scsi_sense_tail].SenseKey = skey;
    msc->scsi_sense[msc->scsi_sense_tail].ASC = asc << 8U;
    msc->scsi_sense_tail++;

    if (SENSE_LIST_DEEPTH == msc->scsi_sense_tail) {
        msc->scsi_sense_tail = 0U;
    }
}
V1.3.0:
void scsi_sense_code (usb_dev *udev, uint8_t lun, uint8_t skey, uint8_t asc)
{
    usbd_msc_handler *msc = (usbd_msc_handler *)udev->class_data[USBD_MSC_INTERFACE];

    msc->scsi_sense[msc->scsi_sense_tail].SenseKey = skey;
    msc->scsi_sense[msc->scsi_sense_tail].ASC = asc;
    msc->scsi_sense_tail++;

    if (SENSE_LIST_DEEPTH == msc->scsi_sense_tail) {
        msc->scsi_sense_tail = 0U;
    }
}

Fix file:
NONE
fix reason: 
Add dual buffer examples for CDC/MSC/AUDIO.

V1.2.0:
NONE
V1.3.0:
NONE
	
Fix file:
/fw3233/GD32E51x_Firmware_Library/Firmware/GD32E51x_usbhs_library/driver/Source/drv_usb_dev.c
fix reason: 
Fix the issue where the enum_speed parameter may cause an array out-of-bounds error.



V1.2.0:
    uint8_t enum_speed = udev->regs.dr->DSTAT & DSTAT_ES;
V1.3.0:
    uint8_t enum_speed = ((udev->regs.dr->DSTAT & DSTAT_ES) >> 1U);
	

Fix file:
NONE
fix reason: 
Add dual buffer examples for CDC/MSC/AUDIO.

V1.2.0:
NONE
V1.3.0:
NONE
	
Fix file:
/fw3233/GD32E51x_Firmware_Library/Firmware/GD32E51x_usbd_library/device/Source/usbd_core.c
/fw3233/GD32E51x_Firmware_Library/Firmware/GD32E51x_usbd_library/device/Source/usbd_enum.c
fix reason: 
Modify the firmware library and pass the self-powered CVTest

V1.2.0:
            } else {
                status[0] = 0U;
            }
V1.3.0:
NONE

V1.2.0:
NONE
V1.3.0:
     /* configure power management */
    udev->dev.pm.power_mode = (udev->dev.desc->config_desc[7] & BIT(6)) >> 6;


Fix file:
/fw3233/GD32E51x_Firmware_Library/Firmware/GD32E51x_usbhs_library/driver/Source/drv_usbh_int.c
fix reason: 
The out processing of the channel in the drv_usbh_int.c file of the host causes usb_pp_halt twice. Delete the redundant usb_pp_halt function.

V1.2.0:
        usb_pp_halt(udev, (uint8_t)pp_num, HCHINTF_NAK, PIPE_NAK);
V1.3.0:
NONE

__________________________________________________________________________________________________________________________



______________________RCU_______________________________________________________________________________________________
Fix file:
/fw3233/GD32E51x_Firmware_Library/Firmware/GD32E51x_standard_peripheral/Include/gd32e51x_rcu.h
fix reason: 
RCU_USBD add GD32EPRTxxA macro define
V1.2.0:
#if defined(GD32E51X_HD)

V1.3.0:
#if (defined(GD32E51X_HD)|| defined(GD32EPRTxxA))

Fix file:
/fw3233/GD32E51x_Firmware_Library/Firmware/GD32E51x_standard_peripheral/Include/gd32e51x_rcu.h
fix reason: 
EPRTxxxA include ENET module, rcu_periph_reset_enum include ENET
V1.2.0:
#if (defined(GD32E51X_CL) || defined(GD32E518))

V1.3.0:
#if (defined(GD32E51X_CL) || defined(GD32E518) || defined(GD32EPRTxxA))




__________________________________________________________________________________________________________________________




______________________USART_______________________________________________________________________________________________
Fix file:
/fw3233/GD32E51x_Firmware_Library/Examples/USART/Half_duplex_transmitter&receiver/main.c
/fw3233/GD32E51x_Firmware_Library/Examples/USART/Half_duplex_transmitter&receiver/readme.txt
fix reason: 
Modify TX pin to open-drain output
V1.2.0:
    /* configure the USART0 Tx pin and USART1 Tx pin */
    gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_9);
    gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2);

V1.3.0:
    /* configure the USART0 Tx pin and USART1 Tx pin */
    gpio_init(GPIOA, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_9);
    gpio_init(GPIOA, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_2);





__________________________________________________________________________________________________________________________

______________________RTC_______________________________________________________________________________________________
Fix file:
/fw3233/GD32E51x_Firmware_Library/Examples/RTC/Calendar_demo/main.c
fix reason: 
Add clear RCU_BDCTL_BKPRST flag
V1.2.0:
int main(void)
{
    /* COM0 configuration */
    gd_eval_com_init(EVAL_COM0);

    /* NVIC configuration */
    nvic_configuration();

    printf("\r\n This is a RTC demo...... \r\n");

    /* get RTC clock entry selection */
    RTCSRC_FLAG = GET_BITS(RCU_BDCTL, 8, 9);

    if((0xA5A5 != bkp_read_data(BKP_DATA_0)) || (0x00 == RTCSRC_FLAG)) {
        /* backup data register value is not correct or not yet programmed
        (when the first time the program is executed) */
        printf("\r\nThis is a RTC demo!\r\n");
        printf("\r\n\n RTC not yet configured....");

V1.3.0:
int main(void)
{
    /* COM0 configuration */
    gd_eval_com_init(EVAL_COM0);

    /* NVIC config */
    nvic_configuration();
    
    /* enable PMU and BKPI clocks */
    rcu_periph_clock_enable(RCU_BKPI);
    rcu_periph_clock_enable(RCU_PMU);
    /* allow access to BKP domain */
    pmu_backup_write_enable();
    if(RESET != (RCU_BDCTL & RCU_BDCTL_BKPRST)) {
        rcu_bkp_reset_disable();
    }
    
    /* get RTC clock entry selection */
    RTCSRC_FLAG = GET_BITS(RCU_BDCTL, 8, 9);

    printf( "\r\n This is a RTC demo...... \r\n" );

    if((0xA5A5 != bkp_read_data(BKP_DATA_0)) || (0x00 == RTCSRC_FLAG)) {
        /* backup data register value is not correct or not yet programmed
        (when the first time the program is executed) */
        printf("\r\nThis is a RTC demo!\r\n");
        printf("\r\n\n RTC not yet configured....");

___________________________________________________________________________________________________________

